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2. CARTRIDGE CONNECTORS
Pin
49
1
Pin
50
2
Pin
Name
l/O
Pin
Name
l/O
1
CSI
O
2
CS2
O
3
CS12
0
4
SLTSL
O
5
Reserve
—
6
RFSH
O
7
WAIT
1
8
INT
1
9
Ml
O
10
BUSDIR
1
11
IORQ
O
12
MERQ
O
13
WR
O
14
RD
0
15
RESET
0
16
Reserve
17
A9
o
18
Al 5
o
19
Al 1
0
20
AIO
0
21
A7
0
22
A6
o
23
A12
0
24
A8
o
25
A14
0
26
A13
0
27
Al
0
28
A0
o
29
A3
o
30
A2
0
31
A5
o
32
A4
o
33
Dl
l/O
34
DO
l/O
35
D3
l/O
36
D2
l/O
37
D5
l/O
38
D4
l/O
39
D7
l/O
40
D6
l/O
41
GND
-
42
CLOCK
o
43
GND
-
44
SW1
_
45
+ 5V
-
46
SW2
_
47
+ 5V
-
48
+ 12V
__
49
SOUNDIN
1
50
- 12V
-
Pin
Name
Content
1
CSI
2
CS2
3
CSI 2
4
SLTSL
5
Reserve
6
RFSH
7
WAIT
8
INT
9
Ml
10
BUSDIR
11
IORQ
12
MERQ
13
WR
14
RD
15
RESET
16
Reserve
17-32
A0-Al'
ROM addresses 4000 — 7FFF select signal
ROM addresses 8000 ~ BFFF select signal
ROM addresses 4000 - BFFF select signal (tor 256k ROM)
Slot select signal
Reserved signal line - use inhibited
Refresh cycle signal
CPU's WAIT request signal
Interrupt request signal to CPU
Signal expressing CPU fetch cycle
This signal Controls direction ot external data bus buffer
Cartridges are selected and L level is output from each
cartridge at data transmission time
l/O request signal
Memory request signal
Write timing signal
Read timing signal
System reset signal
Reserved signal line ~ use inhibited
Address bus signals
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