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3. INSTEEKMODULE-AANSLUITINGEN
Pin
Name
cs
1
cs12
3
Reserve
5
7
WAIT
Mi
9
11
IORG
13
WR
RESET
15
17
A9
19
A11
21
A7
A12
23
25
A14
27
A1
29
A3
31
A5
33
Dt
35
D3
37
D5
39
D7
a
GND
43
GND
+5V
45
+5V
47
49
SOUNDIN
Pin
Name
csi
1
cs2
2
cs12
3
SLTSL
4
5
Reserve
6
RFSH
7
WAIT
8
INT
Mi
9
10
BUSDIR
11
12
13
14
15
16
17-32
28
vo
0
o
-
1
°
0
o
o
o
o
o
o
o
o
o
o
vo
vo
vo
vo
-
-
-
-
1
Content
addresses
ROM
4000
addresses
ROM
8000
addresses
4000
ROM
select
Slot
signal
line
Reserved
signal
Refresh cycle signal
CPU's
signal
WAIT
request
signal to
Interrupt
request
Signal
expressing
CPU
This signal controls direction
Cartridges are selected and
cartridge at data transmission time
request
signal
VO
request
signal
Memory
Write
timing signal
Read timing signal
signal
System
reset
line
Reserved
signal
bus
Address
signals
Pin
Name
€82
2
SLTSL
4
6
RFSH
8
INT
10
BUSDIR
12
MERQ
14
RD
Reserve
16
18
A15
20
A10
2
A6
24
A8
26
A13
28
AO
30
A2
32
A4
34
DO
36
D2
38
D4
40
D6
42
CLOCK
44
Sw1
Sw2
46
+12V
48
50
—12V
select
7FFF
signal
—
select
signal
BFFF
—
select
signal
—BFFF
inhibited
use
—
CPU
fetch cycle
data bus
external
of
level
is output
use
inhibited
—
vo
0
o
0
1
1
o
[eo]
-
[eo]
o
o
o
[eo]
o
[e]
o
vo
vo
vo
vo
[e]
-
=
=
-
(for 256k
ROM)
buffer
each
from
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