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Advertenties
L
4. INSTEEKMODULE-AANSLUITINGEN
Pin
Pin
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
al
43
45
47
49
Pin
1
ë
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17-32
49
!
50
vo
Name
Ts
o
o
cs12
Reserve
=
WAIT
1
o
MI
0
IORG
WR
0
o
RESET
o
A9
o
A11
o
A7
o
A12
o
A14
o
A1
o
A3
o
A5
vo
D1
vo
D3
vo
D5
vo
D7
GND
=
GND
=
+5V
=
-
+5V
SOUNDIN
1
Content
Name
csi
ROM
cs2
ROM
€12
ROM
SLTSL
Slot
Reserve
Reserved
Refresh cycle signal
RFSH
CPU's
WAIT
Interrupt
INT
Mi
Signal expressing
This signal controls direction
BUSDIR
Cartridges
cartridge at data transmission time
VO
Memory
Write
WR
Read
_
RD
RESET
System reset signal
Reserve
Reserved
Address
A0
A15
—
Z
Pin
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
addresses
4000
—
addresses
8000
—
addresses
4000
—BFFF
select
signal
line
signal
use
—
request
signal
WAIT
signal to
request
CPU
are
selected and
request
signal
request
signal
timing signal
signal
timing
line
signal
use
—
bus signals
1
2
Name
2
4
6
INT
8
BUSDIR
MERQ
RD
Reserve
A15
A10
A6
Ag
A13
AO
A2
A4
DO
D2
D4
D6
CLOCK
Sw1
sw2
+12V
—12V
select signal
7FFF
select
signal
BFFF
select
(for
signal
inhibited
CPU
fetch cycle
external data
of
is
level
output
inhibited
vo
o
o
o
1
1
°
°
=
o
o
o
o
o
o
o
o
vo
vo
vo
vo
o
-
"
=
=
256k
ROM)
buffer
bus
each
from
49
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