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CARTRIDGE CONNECTORS
2.
Pin
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
43
45
47
49
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17-32
28
50
vo
Name
0
CSI
o
cs12
-
Reserve
WAIT
1
o
Mi
o
iORQ
o
WR
o
RESET
o
A9
o
A11
o
A7
o
A12
A14
[eo]
o
A1
o
A3
o
A5
vo
D1
vo
D3
vo
D5
vo
D7
-
GND
-
GND
+5V
=
+5V
u
SOUNDIN
1
Content
Name
cs1
ROM
cs2
ROM
cs12
ROM
SLTSL
Slot
Reserve
Reserved
Refresh cycle signal
RFSH
CPU's
WAIT
INT
Interrupt
Mi
Signal expressing
BUSDIR
This signal controls direction
Cartridges are selected and
cartridge at data transmission time
IORG
VO
MERG
Memory
Write timing
WR
Read timing signal
RD
RESET
System reset signal
Reserve
Reserved
—A15
Address bus signals
A0
Pin
2
4
6
8
10
12
14
16
18
20
2
24
26
28
30
32
34
36
38
40
42
44
46
48
50
addresses
4000
7FFF
—
addresses
8000
—
addresses
4000
-BFFF
select signal
line
use
signal
—
WAIT
request signal
request
signal to
fetch cycle
CPU
request signal
request
signal
signal
line
use
signal
—
2
select
signal
select signal
BFFF
select
signal
(for 256k
inhibited
CPU
external data
of
is output
level
from
L
inhibited
vo
o
°
o
1
1
°
o
-
o
o
o
o
o
o
o
o
vo
vo
vo
vo
o
-
-
-
-
ROM)
bus
buffer
each
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